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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICV_EOIR, Virtual Machine End Of Interrupt Register</h1><p>The GICV_EOIR characteristics are:</p><h2>Purpose</h2>
        <p>A write to this register performs a priority drop for the specified Group 0 virtual interrupt and, if <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EOImode == 0, also deactivates the interrupt.</p>

      
        <p>This register corresponds to the physical CPU interface register <a href="ext-gicc_eoir.html">GICC_EOIR</a>.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICV_EOIR are <span class="arm-defined-word">RES0</span>.</p>
        <p>This register is available when the GIC implementation supports interrupt virtualization.</p>
      <h2>Attributes</h2>
        <p>GICV_EOIR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="7"><a href="#fieldset_0-31_25">RES0</a></td><td class="lr" colspan="25"><a href="#fieldset_0-24_0">INTID</a></td></tr></tbody></table><h4 id="fieldset_0-31_25">Bits [31:25]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-24_0">INTID, bits [24:0]</h4><div class="field"><p>The INTID of the signaled interrupt.</p>
<div class="note"><span class="note-header">Note</span><p>INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.</p></div><p>When affinity routing is not enabled:</p>
<ul>
<li>Bits [23:13] are <span class="arm-defined-word">RES0</span>.
</li><li>For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are <span class="arm-defined-word">RES0</span>.
</li></ul></div><div class="text_after_fields"><p>The behavior of this register depends on the setting of <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EOImode:</p>
<table class="valuetable"><thead><tr><th><a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EOImode</th><th>Behavior</th></tr></thead><tbody><tr><td><span class="binarynumber">0b0</span></td><td>Both the priority drop and the deactivate interrupt effects occur</td></tr><tr><td><span class="binarynumber">0b1</span></td><td>Only the priority drop effect occurs.</td></tr></tbody></table>
<p>A successful EOI request means that:</p>
<ul>
<li>The highest priority bit in <a href="ext-gich_aprn.html">GICH_APR&lt;n&gt;</a> is cleared, causing the running priority to drop.
</li><li>If the appropriate <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EOImode bit == 0, the interrupt is deactivated in the corresponding List register <a href="ext-gich_lrn.html">GICH_LR&lt;n&gt;</a>. If <a href="ext-gich_lrn.html">GICH_LR&lt;n&gt;</a>.HW == 1, indicating the INTID corresponds to a hardware interrupt, a deactivate request is also sent to the physical Distributor, identifying the physical INTID from the corresponding field in the List register. This effect is identical to a Non-secure write to <a href="ext-gicc_dir.html">GICC_DIR</a> from the PE having that physical INTID. This means that if the corresponding physical interrupt is marked as Group 0, and <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 0, the deactivation request is ignored. See <a href="ext-gicc_eoir.html">GICC_EOIR</a> for more information.
</li></ul>
<div class="note"><span class="note-header">Note</span><p>Only Group 1 interrupts can target the hypervisor, and therefore only Group 1 interrupts are deactivated in the Distributor.</p></div></div><h2>Accessing GICV_EOIR</h2>
        <p>This register is used only when System register access is not enabled. When System register access is enabled:</p>

      
        <ul>
<li>For AArch32 implementations, <a href="AArch32-icc_eoir0.html">ICC_EOIR0</a> provides equivalent functionality.
</li><li>For AArch64 implementations, <a href="AArch64-icc_eoir0_el1.html">ICC_EOIR0_EL1</a> provides equivalent functionality.
</li></ul>

      
        <p>This register is used for Group 0 interrupts only. <a href="ext-gicv_aeoir.html">GICV_AEOIR</a> provides equivalent functionality for Group 1 interrupts.</p>

      
        <p>When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.</p>
      <h4>GICV_EOIR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Virtual CPU interface</td><td><span class="hexnumber">0x0010</span></td><td>GICV_EOIR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">WO</span>.
          </li><li>When an access is Secure, accesses to this register are <span class="access_level">WO</span>.
          </li><li>When an access is Non-secure, accesses to this register are <span class="access_level">WO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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